Nonvolatile semiconductor memory device and method of manufacturing the same

ABSTRACT

A nonvolatile semiconductor memory device comprising: a semiconductor substrate ( 20 ); and a memory transistor ( 100 ) including a source region ( 20 S) and a drain region ( 20 D) which are impurity diffusion layers formed in the semiconductor substrate, a tunnel insulating layer ( 25 ) formed on the semiconductor substrate, and a staked-structure gate electrode ( 20 G) having a floating gate ( 24 ), a dielectric layer ( 23 ) and a control gate ( 22 ) which are layered on the tunnel insulating layer. The floating gate ( 24 ) is formed of a polysilicon layer having an impurity concentration of 1×10 19  to 1×10 20  cm −3 . Denoting the impurity concentration of a polysilicon layer constituting the floating gate ( 24 ) as C FG  and the impurity concentration of a polysilicon layer constituting the control gate ( 22 ) as C CG , it is preferable that the following relational expression (1) be satisfied: 
     
       
         0.3×C FG ≦C CG ≦0.8×C FG    
       
     
     In the nonvolatile semiconductor memory device in the present invention, an impurity concentration of the polysilicon layer constituting the floating gate is in a specific range for preventing deterioration of the film quality of the tunnel insulating layer due to impurities contained in the floating gate, thereby making it possible to enhance characteristics such as an erase characteristic and a data retaining characteristic.

TECHNICAL FIELD

The present invention relates to a nonvolatile semiconductor memorydevice and a method of manufacturing the same. More particularly, thepresent invention pertains to a nonvolatile semiconductor memory devicefeaturing performance of flash erasure of memory transistors and reducedvariation in erase operation time, and a manufacturing method thereof.

BACKGROUND OF ART

A flash-type EEPROM contains a multiplicity of memory transistors. FIG.16 shows a schematic sectional view of one of these memory transistors.A memory transistor 200 comprises a source region 55 and a drain region56, which are impurity diffusion layers formed in a semiconductorsubstrate 50, and a tunnel oxide film 51, a floating gate 52, adielectric layer 53, and a control gate 54 which are layered on thesemiconductor substrate 50. On the side areas of the layered floatinggate 52, dielectric layer 53 and control gate 54, there is provided aside wall 57 made of an insulating material.

In the memory transistor 200, information is programmed by injectingelectrons 58 into the floating gate 52 (which is a write operation,indicated by an arrow 59 in FIG. 16) and by drawing the electrons fromthe floating gate 52 (which is an erase operation, indicated by an arrow59′ in FIG. 16).

In the flash-type EEPROM, an erase operation is performed on a pluralityof memory transistors entirely. In most cases, erasure is carried out onthe entire EEPROM or on each page corresponding to a group of pluralmemory transistors. For example, an erase operation is accomplished asdescribed below.

A source voltage Vs, which is a high potential (e.g., 12 V), is appliedto the source region 55. At this step, the control gate 54 and thesemiconductor substrate 50 have a ground potential, and the drain region56 is open. In this state, electrons 58 stored in the floating gate 52are drawn into the source region 55 through the thin tunnel oxide film51 by means of the Fowler-Nordheim tunnel, as indicated by the arrow 59′in FIG. 16. This results in a threshold voltage Vg of the memorytransistor 200 being equal to a threshold voltage level of a common MOStransistor.

In the flash-type EEPROM used as a storage device, it is desirable thatthe erase operation mentioned above should be carried out at higherspeed. Namely, a period of time required for a flash erase operation(i.e., an erase characteristic) is of critical importance in theflash-type EEPROM.

Further, the erase characteristic is required to be uniform amongrespective memory elements. If the erase characteristic is not uniformamong the memory elements, a malfunction may occur in the memory elementto cause various problems as mentioned below.

For instance, when the time required for erasure in some memorytransistors is longer than a predetermined erase operation time,electrons remain stored in the floating gates of these memorytransistors. This condition is called “under-erasure”. On the contrary,when the time required for erasure in some memory transistors is shorterthan a predetermined erase operation time, electrons are drawnexcessively from the floating gates of these memory transistors. Thiscondition is called “over-erasure”.

In the case where the degree of variation in the erase characteristic issmall among the memory transistors, it is possible to select an eraseoperation time “T” that allows proper erasure of any memory transistors.However, in case that the degree of variation in the erasecharacteristic is large, there is a substantial possibility thatunder-erasure or over-erasure may occur at some cells. Further, in thecase where the degree of variation in the erase characteristic isextremely large, under-erasure or over-erasure will occur inevitably insome memory transistors, no matter what erase operation time “T” maybeselected. Thus, it becomes impossible to perform proper erasure in anymemory transistors.

For realizing a high-speed flash-type EEPROM, it is required to decreasethe erase operation time “T” insofar as possible. Since erasure isperformed by drawing electrons from the floating gate 52 to the sourceregion 55 as described above, a higher-speed erase operation may beachieved by increasing an overlapping area of the floating gate 52 andthe source region 55. When the overlapping area is too large, however, aproblem such as a malfunction may be prone to occur.

Therefore, for a realization of the high-speed flash-type EEPROM, it isrequired to increase the overlapping area of the source region andfloating gate to the extent that no malfunction will occur, whileminimizing the degree of variation in the overlapping area amongrespective memory transistors.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a nonvolatilesemiconductor memory device comprising a memory transistor having auniform erase characteristic to enable high-speed flash erasure, and amethod of manufacturing the same.

As one aspect of the present invention, there is provided a nonvolatilesemiconductor memory device, comprising:

a semiconductor substrate; and

a memory transistor including a source region and a drain region whichare impurity diffusion layers formed in the semiconductor substrate, atunnel insulating layer formed on the semiconductor substrate, and agate electrode of a stacked structure having a floating gate, adielectric layer and a control gate which are layered on the tunnelinsulating layer,

wherein the floating gate is formed of a polysilicon layer having animpurity concentration of 1×10¹⁹ to 1×10²⁰ cm⁻³.

In the nonvolatile semiconductor memory device mentioned above, since animpurity concentration of the polysilicon layer constituting thefloating gate is in a specified range, deterioration of the film qualityof the tunnel insulating layer due to impurities contained in thefloating gate can be prevented, and it is possible to improve an erasecharacteristic and a data retaining characteristic. Further, theimpurity concentration of the polysilicon layer constituting thefloating gate is preferably in a range of 1×10¹⁹ to 5×10¹⁹ cm⁻³.

Denoting the impurity concentration of a first polysilicon layerconstituting the floating gate as C_(FG) and the impurity concentrationof a second polysilicon layer constituting the control gate as C_(CG),it is preferable that the following relational expression be satisfied:

0.3×C_(FG)≦C_(CG)≦0.8×C_(FG)

By setting up the above relationship, the impurity concentrations of thepolysilicon layers constituting to the floating gate and the controlgate approximate each other. Consequently, in forming an electrodecomprising the floating gate, dielectric layer, and control gate bymeans of etching, the end portion of each layer can be aligned in thethickness direction to allow formation of an ideal stacked-structuregate electrode. According to the inventors of the present invention, ithas been confirmed that such an ideal stacked gate structure greatlycontributes to an improvement in the data retaining characteristic, forexample.

In the source region, an overlapping region with the floating gate ispreferably 25 to 45% of a bottom surface of the floating gate. Ahigh-speed erasure can be possible by such an arrangement that thesource region and the floating gate are formed to sufficiently overlapeach other to the proper extent that a malfunction can be prevented.

Further, the source region preferably comprises a first diffusion regionhaving a high impurity concentration, and a second diffusion regiondisposed outside the first diffusion region and having an impurityconcentration lower than that of the first diffusion region. In such anarrangement that the source region is formed in a double diffusionstructure, it becomes possible to control the transfer rate of electronsto move from the floating gate to the source region.

As another aspect of the present invention, there is provided a methodof manufacturing a nonvolatile semiconductor memory device, comprisingsteps of:

(a) forming a tunnel insulating layer, a first polysilicon layer for afloating gate, a dielectric layer, and a second polysilicon layer for acontrol gate in a memory transistor formation region on a semiconductorsubstrate;

(b) forming a gate electrode of a stacked structure including a floatinggate, a dielectric layer, and a control gate by patterning the secondpolysilicon layer, the dielectric layer, and the first polysiliconlayer; and

(c) forming a source region and a drain region in the semiconductorsubstrate by doping with an impurity;

wherein, in the step (a), the first polysilicon layer is doped with animpurity at a concentration of 1 ×10¹⁹ to 1×10²⁰ cm⁻³.

Further, a concentration of the impurity is preferably in a range of1×10¹⁹ to 5×10¹⁹ cm⁻³.

A dose for attaining such an impurity concentration as indicated abovedepends on the film thickness of the polysilicon layer, and thereforecannot be defined conclusively. For example, where the first polysiliconlayer has a film thickness of 80 to 200 nm, it is formed by doping apolysilicon layer with a dose of an impurity ion preferably in a rangeof 1×10¹⁴ to 1×10¹⁵ cm⁻², or more preferably in a range of 1 ×10¹⁴ to5×10¹⁵ cm⁻².

In the semiconductor device manufacturing method of the presentinvention, it is further preferable to comprise a step (d), before thestep (c), for forming a protective oxide layer to cover exposed surfaceof at least the tunnel insulating layer and gate electrode.

Since an impurity concentration of the first polysilicon layer is set atthe range indicated above in the step (a), the film thickness of theprotective oxide film formed at least on an exposed surface (side wall)of the floating gate can be decreased at the step (d). This makes itpossible to provide advantageous effects as mentioned below.

In general, a protective oxide film formed on an exposed surface of thefloating gate by means of thermal oxidation, for example, has athickness of 15 to 20 nm. The overlap area of the floating gate and thesource region is reduced by this thickness of the protective oxide film.However, by making the impurity concentration of the first polysiliconlayer lower than that in common practice at the step a), the thicknessof the protective oxide film formed on the exposed surface of thefloating gate can be made to a range of 5 to 15 nm or more preferably toa range of 8 to 12 nm. Thus, the overlapping area of the floating gateand the source region (effective area of the tunnel insulating layer)may be enlarged uniformly, making it possible to improve the erasecharacteristic.

Representative examples of nonvolatile semiconductor memory devices ofthe present invention include an erasable programmable read-only memory(EPROM), electrically erasable programmable read-only memory (EEPROM),flash EEPROM, embedded memory containing any of these nonvolatilememories, programmable logic device (PLD), and the like.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic sectional view of an example of a memorytransistor in a flash-type EEPROM to which a nonvolatile semiconductormemory device of the present invention is applies.

FIG. 2. is a schematic sectional view illustrating a manufacturing stepof the memory transistor indicated in FIG. 1.

FIG. 3 is a schematic sectional view illustration manufacturing step ofthe memory transistor indicted i FIG. 1.

FIG. 4 is a schematic sectional view illustrating a manufacturing stepof the memory transistor indicated in FIG. 1.

FIG. 5 is a schematic sectional view illustrating a manufacturing stepof the memory transistor indicated in FIG. 1.

FIG. 6 is a schematic sectional view illustrating a manufacturing stepof the memory transistor indicated in FIG. 1.

FIG. 7 is a schematic sectional view illustrating a manufacturing stepof the memory transistor indicated in FIG. 1.

FIG. 8 illustrates a relationship between a dose of a impurity ion andan erase characteristic.

FIG. 9. Illustrates a relationship between the dose of the impurity ionand a gate disturbance characteristic.

FIG. 10 illustrates a Fowler-Nordheim plot when an erase operation isperformed.

FIG. 11 illustrates a Fowler-Nordheim plot when a write operation isperformed.

FIG. 12 illustrates a Fowler-Nordheim plot when an erase operation isperformed.

FIG. 13 illustrates a Fowler-Nordheim plot when a write operation isperformed.

FIG. 14 illustrates a relationship between a dose in a floating gate anda quantity of passing charge allowable until occurrence of a breakdownof a tunnel oxide film.

FIG. 15 illustrate a relationship between a data retainingcharacteristic of a memory cell and the dose in the floating gate.

FIG. 16 is a schematic sectional view of a example of a common memorytransistor in a flash-type EEPROM.

BEST MODE FOR CARRYING OUT THE INVENTION Semiconductor Device

FIG. 1 shows a schematic sectional view of an example of a memorytransistor in a flash-type EEPROM to which a nonvolatile semiconductormemory device of the present invention is applied.

A memory transistor 100 comprises a field oxide region 21 and a tunneloxide film (tunnel insulating layer) 25 formed on a P-type semiconductorsubstrate 20. On the tunnel oxide film 25, there are layered a floatinggate 24, a three-layer-structure ONO film (dielectric layer) 23 formedof a silicon oxide film, a silicon nitride film and a silicon oxidefilm, and a control gate 22 to provide a gate electrode 20G of a stackedstructure.

In the semiconductor substrate 20, a source region 20S and a drainregion 20D are formed at both sides of the gate electrode 20G. Thesource region 20S comprises a first N⁺ type diffusion region 26 having ahigh impurity concentration and a second N⁻ type diffusion region 27disposed outside the first diffusion region and having an impurityconcentration lower than that of the first diffusion region 26. Thedrain region 20D comprises a first N⁺ type diffusion region 28 having ahigh impurity concentration and a second N⁻ type diffusion region 29which is disposed outside the first diffusion region 28 and having animpurity concentration lower than that of the first diffusion region 29.In this arrangement where the source region 20S is formed in a doublediffusion structure, it is possible to adjust the transfer rate ofelectrons in movement from the floating gate 24 to the source region20S.

The floating gate 24 is formed of a polysilicon layer having an impurityconcentration of 1×10¹⁹ to 1×10²⁰ cm⁻³, preferably of 1×10¹⁹ to 5 ×10¹⁹cm⁻³. Since the impurity concentration of the polysilicon layerconstituting the floating gate 24 is in the specific range indicatedabove, deterioration of the film quality of the tunnel insulating layerdue to impurities contained in the floating gate 24 can be prevented,and characteristics such as an erase characteristic, a gate disturbancecharacteristic, and a data retaining characteristic can be improved.Data for these characteristics will be described later.

Further, by setting the impurity concentration of the polysilicon layerconstituting the floating gate 24 in the specific range indicated above,the thickness of a protective oxide film formed on an exposed surface(side wall) of the floating gate can be thinner as described later. As aresult, the overlapping area of the floating gate 24 and the sourceregion 20S can be wider by a decreased thickness of the protective oxidefilm, and making it possible to increase the effective area of thetunnel insulating layer. Still further, by setting the impurityconcentration of the polysilicon layer constituting the floating gate 24in the specific range indicated above, it is possible to decrease thedegree of variation in the thickness of the protective oxide film formedon the exposed surface (side wall) of the floating gate. This reducesthe degree of variation in the overlapping area of the floating gate 24and the source region 20S, thereby making it possible to provide auniform erase characteristic.

Denoting the impurity concentration of a first polysilicon layerconstituting the floating gate 24 as C_(FG) and the impurityconcentration of a second polysilicon layer constituting the controlgate 22 as C_(CG), it is preferable that the following relationalexpression (1) be satisfied:

0.3×C_(FG)≦C_(CG) ≦0.8×C _(FG)   (1)

Under this relational condition, the impurity concentration of thepolysilicon layer constituting the floating gate 24 is lower than orapproximately equal to that of the polysilicon layer constituting thecontrol gate 22. Thus, in etching the floating gate, ONO film, andcontrol gate layers, the end portion of these layers can be aligned inthe thickness direction so that an ideal stacked structure for the gateelectrode 20G can be obtained.

The control gate 22 is preferably formed in a known polycide structurehaving a metallic silicide layer on a doped polysilicon layer forenhancing conductivity.

In the source region 20S, a region 30 overlapping the floating gate 24is preferably 25 to 45% of the bottom surface of the floating gate 24.By overlapping the source region 20S and the floating gate 24 oneanother to a broad extent, electrons can be quickly drawn from thefloating gate 24 to the source region 20S, thereby enabling a high-speederase operation.

Semiconductor Device Manufacturing Method

Referring to FIGS. 2 to 7, schematic sectional views are shown forexplaining the manufacturing steps of the memory transistor 100indicated in FIG. 1.

(A) As shown in FIG. 2, a field oxide film 21 is formed on asemiconductor substrate 20, and then a tunnel oxide film 25 is formed onthe semiconductor substrate 20. For formation of the field oxide film21, a known technique is applicable. For formation of the tunnel oxidefilm 25, oxidation is carried out in a dry oxygen atmosphere at anoxidizing temperature of approx. 750 to 1000° C. or in a wet oxygenatmosphere at an oxidizing temperature of approx. 750 to 850° C. Thetunnel oxide film 25 thus formed is approx. 6 to 12 nm thick.

(B) Then, as shown in FIG. 3, a first polysilicon layer 400 to be afloating gate is deposited. Deposition of the first polysilicon layer400 can be performed by a chemical vapor deposition (CVD) method, forexample, using monosilane (SiH₄) as a material gas under a temperatureof 550 to 620° C. The first polysilicon layer 400 is preferably 80 to200 nm thick, or more preferably 100 to 130 nm thick.

Further, to provide conductivity to the first polysilicon layer 400,arsenic or its compound is ion implanted into the first polysiliconlayer 400. This ion implantation is carried out under conditions thatthe implanting voltage is 20 to 30 keV and the dose is 1×10¹⁴ cm⁻² to1×10¹⁵ cm⁻². Besides arsenic, any other substance capable of providingN-type conductivity such as phosphorus may be used as an impurity forion implantation.

In the present embodiment, ion implantation is performed with thepolysilicon layer 400 directly exposed. Instead of this method, aso-called “through implant” technique may be adopted. In this technique,for preventing the polysilicon layer from being damaged by ionimplantation, a thin oxide film or the like is formed on the polysiliconlayer. Using the thin oxide film as a transmission film, the kineticenergy of ions to be implanted is controlled so that the ions will beimplanted into a desired layer only.

In this process step, the use of ion implantation method is advantageousin that the concentration of doped impurity can be made lower than withother technique. In case a protective oxide film is formed by means ofthermal oxidation at a step to be taken before the subsequent step offorming source and drain regions, a protective oxide film on a side-wallof a gate electrode tends to be thicker than a protective oxide film ona principal surface due to the effect of impurity ions. Therefore, inthe present invention, the impurity concentration of the firstpolysilicon layer 400 for the floating gate is reduced so that aside-wall protective oxide film formed on the floating gate by thermaloxidation will be as thin as possible.

In formation of the polysilicon layer 400, as an impurity doping methodother than ion implantation, any of the following techniques may beemployed; a method of introducing carrier gas containing phosphorylchloride (POCl₃) after forming the polysilicon layer, a method ofintroducing carrier gas containing phosphine (PH₃) at the formation ofthe polysilicon layer, and the like.

Thereafter, anisotropic photoetching is carried out to etch thepolysilicon layer 400. Thus, apart of the polysilicon layer 400 is leftto form the floating gate.

(C) Then, as shown in FIG. 4, an ONO film (oxide film —nitridefilm—oxide film) 500 used as a dielectric layer is formed. For example,a thermal oxidation method or a CVD method can be used for oxide filmdeposition, and a CVD method can be used for nitride film deposition. Inthe ONO film 500, the lowermost-layer oxide film is 6 to 20 nm thick,the nitride film is 8 to 20 nm thick, and the uppermost-layer oxide filmis 2 to 6 nm thick. The total thickness of the ONO film 500 ispreferably approx. 10 to 40 nm (in terms of oxide film thickness).

Subsequently, a second polysilicon layer 600 to be a control gate isdeposited under the same conditions as for formation of the firstpolysilicon layer 400 to be the above-mentioned floating gate. Asdescribed in the foregoing, it is preferable that the second polysiliconlayer 600 contains impurities at a concentration satisfying therelational expression (1) with respect to the first polysilicon layer400.

(D) Then, as shown in FIG. 5, a photoresist is applied on the secondpolysilicon layer 600, and the photoresist is patterned to form a resistlayer (not shown). Then, using this resist layer as a mask, the secondpolysilicon layer 600 is etched to form the control gate 22. For thisetching, it is preferable to use anisotropic dry etching.

Subsequently, using the control gate 22 as a mask, etching is carriedout in a self-alignment manner to form an ONO film 23 and a floatinggate 24. For this etching, it is also preferable to use anisotropic dryetching.

In this step, lateral dimensional processing accuracy, i.e., allowableerror of gate length or width with respect to a specified designdimension is approx. ±0.03 to 0.05 μm.

(E) Then, as shown in FIG. 6, a protective oxide film 19 is formed onthe surface of the wafer, i.e., on the surface of the tunnel oxide film25, gate electrode 20G, and field oxide film 21. The protective oxidefilm 19 serves to prevent possible damage to the principal surface ofthe semiconductor substrate 20 and the tunnel oxide film 25 during ionimplantation at the subsequent step (F). It also serves to suppress aninfluence caused by energy spread during ion implantation. Theprotective oxide film 19 may be formed by a thermal oxidation method orCVD method, for example.

In case the thermal oxidation method is used, the oxidizing temperatureis set at approx. 800 to 950° C. The thickness of the protective oxidefilm thus formed is approx. 5 to 15 nm. As aforementioned, in thermaloxidation, the protective oxide film on the side wall of the floatinggate 24 tends to be thicker than the protective oxide film on theprincipal surface. However, the concentration of ions to be implanted inthe floating gate 24 is adjusted so that the thickness of the protectiveoxide film on the side wall of the floating gate 24 can be madeapproximately equal to that of the protective oxide film on theprincipal surface. The protective oxide film on the side wall of thefloating gate 24 is preferably 5 to 15 nm thick or more preferably 8 to12 nm thick.

When the CVD method is used, the thickness of the protective oxide filmon the side wall of the floating gate becomes approximately equal tothat of the protective oxide film on the principal surface. Exemplifiedbelow are conditions for depositing an oxide film of a thickness of 5 to15 nm using the CVD method:

Substrate temperature:

350 to 450° C.

Monosilane (SiH₄) gas flow rate:

60 to 90 sccm

Oxygen (O₂) gas flow rate:

400 to 500 sccm

Exemplified below are conditions for depositing an oxide film of athickness of 5 to 15 nm using the high-temperature oxide (HTO):

Substrate temperature:

750 to 850° C.

Pressure:

100 pascals

Monosilane (SiH₄) gas flow rate:

30 to 50 sccm

Nitrogen monoxide (N₂O) gas flow rate:

1500 to 2000 sccm

(F) Then, using the gate electrode 20G as a mask, ion implantation iscarried out to form a source region 20S and a drain region 20D, eachhaving a double diffusion structure. Arsenic, phosphorus or any compoundthereof may be used for ion implantation.

Double-diffusion-structure regions can be formed by a known techniquesuch that plural species of ions are applied in implantation. Forinstance, in each of the source region 20S and the drain region 20D, asecond diffusion region of an N⁻ type can be formed by implanting ionsof a second N type (phosphorus) at a dose of 2×10¹⁴ to 8×10¹⁴ cm⁻² andan accelerating voltage of 50 to 100 keV, and a first diffusion regionof an N⁺ type can be formed by implanting ions of a first N type(arsenic) at a dose of 2×10¹⁵ to 6×10¹⁵ cm⁻² and an accelerating voltageof 40 to 60 keV. By arranging the double diffusion structure in at leastthe source region, it becomes possible to control the transfer rate ofelectrons in drawing from the floating gate.

Then, to ensure an overlapping area of the source region 20S and thefloating gate 24, drive-in diffusion is carried out to activate theimplanted ions so that they will be diffused. The diffusion temperatureis 900 to 950° C. In the source region 20S, the area overlapping thefloating gate 24 is preferably 25 to 45% of the bottom area of thefloating gate 24.

According to operating conditions required for a flash-type EEPROM to bemanufactured, the overlapping area may be determined in the design phasethereof. Since the stacked-structure gate electrode 20G is used as amask in ion implantation as mentioned above, the overlapping area can becontrolled with extremely high accuracy. Further, since the thickness ofthe protective oxide film 19 formed on the side wall of the gateelectrode 20G at the step (E) can be decreased in a certain range, it ispossible to enlarge the overlapping area uniformly. This signifies thatthe degree of variation in the overlay area among respective memorytransistors can be reduced, i.e., the erase characteristic there amongcan be made uniform. Still further, since the overlapping area can bemade wider than in conventional devices, it is possible to decrease thetime required for flash erasure.

In an experiment conducted by the inventors, it has been revealed thatthe flash erasure time in a flash-type EEPROM of the present inventionis as short as approx. 50 ms while that in a flash-type EEPROM for acomparison is approx. 5 ms. In the flash-type EEPROM employed for thecomparison, the thickness of the protective oxide film on the side wallis 18 to 25 nm and the overlapping area of the source region and thefloating gate is 10 to 20% of the bottom of the floating gate.

In the subsequent process steps, common manufacturing methods ofsemiconductor device are applicable.

As mentioned hereinabove, in the present invention, the protective oxidefilm 19 on the side wall of the stacked-structure gate electrode 20G,more particularly on the side wall of the floating gate 24, can be madethinner by decreasing the concentration of impurities in the floatinggate 24. In the case where the impurity concentration of the floatinggate 24 is in the range of 1×10¹⁹ to 1×10²⁰ cm⁻³, the protective oxidefilm 19 on the side wall of the gate electrode 20G can be formed at athickness of approx. 5 to 15 nm. Further, in the case that the impurityconcentration of the floating gate 24 is in the range of 1×10¹⁹ to5×10¹⁹ cm⁻³, the protective oxide film 19 on the side wall of the gateelectrode 20G can be formed at a thickness of 8 to 12 nm. By controllingthe thickness of the protective oxide film 19 on the side wall of thegate electrode 20G, the overlapping area of the source region 20S andthe floating gate 24 can be ensured to increase the effective area ofthe tunnel insulating layer.

Other Preferred Embodiment

After the step (E) in the embodiment mentioned above, there may beprovided a step that the protective oxide film 19 formed in the step (E)is selectively removed at the portion on the side wall of the gateelectrode 20G. For removal of the protective oxide film, an etch-offprocess may be performed using a buffer hydrofluoric acid solution (BHF)prepared by mixing 30% hydrofluoric acid solution (HF) and 30% ammoniumfluoride solution (NH₄F) in a volume ratio of 1:50. Since isotropicetching is carried out with the buffer hydrofluoric acid solution, it isdesirable to use a mask for removing only the protective oxide film onthe side wall of the gate electrode. After a mask having an opening at aportion corresponding to the side wall area of the gate electrode isformed by a known technique, only the protective oxide film on the sidewall is removed by means of etching. This mask may be so formed that theprotective oxide film will be left on the control gate.

With use of this step, it is possible to remove the protective oxidefilm on the side wall of the gate electrode, which would cause adecrease in the overlapping area of the source region and the floatinggate. Thus, the effective area of the tunnel insulating layer can beenlarged uniformly.

Experimental Examples

(a) FIGS. 8 and 9 show the results of an experiment carried out forinvestigating the relationship between a dose of impurity ions forproviding conductivity to the floating gate and an erase characteristicand a relationship between a dose of impurity ions and a gatedisturbance characteristic. In FIG. 8, the abscissa indicates the widthof pulse applied to the source at the time of erasure, and the ordinateindicates the threshold of the gate electrode at the time of erasure. InFIG. 9, the abscissa indicates the width of pulse applied to theselected word line (gate) at the time of writing, and the ordinateindicates the threshold of the non-selected cell gate at the time ofwriting. Each flash-type EEPROM sample employed in this experimentcomprises: the tunnel oxide film of each memory transistor having athickness of 10 nm, the floating gate having a thickness of 130 nm, anddifferent doses of phosphorus impurity being ion implanted at a voltageof 20 keV.

As can be seen from FIG. 8, a decrease in dose increases the speed oferasure, and as shown in FIG. 9, a decrease in dose reduces the tendencyof gate disturbance.

The erase and gate disturbance characteristics contradict one another,i.e., as one is improved, the other worsens. However, as demonstrated inFIGS. 8 and 9, these erase and gate disturbance characteristics can bemade compatible under the condition that a dose of ions implanted intothe floating gate is in the range of 1×10¹⁴ cm⁻² to 1×10¹⁵ cm⁻². Inparticular, under the condition that the dose is in the range of 1×10¹⁴cm⁻² to 5×10¹⁴ cm⁻², these characteristics can satisfactorily be madecompatible.

(b) FIG. 10 shows a Fowler-Nordheim plot when a negative bias voltage isapplied to the gate, i.e., an erase operation is performed. In FIG. 10,the abscissa indicates the reciprocal of electric field intensity, andthe ordinate indicates a Fowler-Nordheim current. The sample used inthis experiment is fabricated in the same manner as for the experiment(a).

In an erase operation, faster erasure is carried out as theFowler-Nordheim current increases. In this respect, it is advantageousto increase the current. As can be seen from FIG. 10, as the dose ofions implanted in the floating gate decreases, the current increases toenhance performance in the erase characteristic.

(c) FIG. 11 shows a Fowler-Nordheim plot when a positive bias voltage isapplied to the gate, i.e., a write operation is performed. In FIG. 11,the abscissa indicates the reciprocal of electric field intensity, andthe ordinate indicates a Fowler-Nordheim current. The sample used inthis experiment is fabricated in the same manner as for the experiment(a).

In a write operation, it is advantageous to decrease the current forpreventing occurrence of a gate disturbance. As can be seen from FIG.11, as the dose of ions implanted in the floating gate decreases, thegate disturbance characteristic improves.

(d) FIG. 12 shows a Fowler-Nordheim plot when a negative bias voltage isapplied to the gate, i.e., an erase operation is performed. In FIG. 12,the abscissa indicates a dose of ions implanted in the floating gate,and the ordinate indicates a Fowler-Nordheim current.

A sample of the flash-type EEPROM memory transistor employed in thisexperiment comprises: the tunnel oxide film having a thickness of 10 nm,the floating gate having a thickness of 130 nm, and different doses ofphosphorus impurity ions implanted at a voltage of 20 keV. The electricfield intensity was 9 MV/cm.

As can be seen from FIG. 12, in an erase operation the Fowler-Nordheimcurrent decreases as the dose increases. With an increase in the dose,the degree of variation increases in the Fowler-Nordheim current. Sincethe erase characteristic is required to be uniform, it is advantageousto minimize the degree of variation in the Fowler-Nordheim current. Inthis respect, the dose in the floating gate is preferably in the rangeof 1×10^(l4) cm⁻² to 1×10¹⁵ cm⁻².

(e) FIG. 13 shows a Fowler-Nordheim plot when a positive bias voltage isapplied to the gate, i.e., a write operation is performed. In FIG. 13,the abscissa indicates a dose in the floating gate, and the ordinateindicates a Fowler-Nordheim current. In this experiment, the sampleemployed is fabricated in the same manner as for the experiment (d).

As can be seen from FIG. 13, in a write operation, the Fowler-Nordheimcurrent increases as the dose increases. With an increase of the dose,the degree of variation increases in the Fowler-Nordheim current. Sincethe write characteristic is required to be uniform, it is desirable tominimize the degree of variation in the Fowler-Nordheim current. In thisrespect, the dose in the floating gate is also preferably in the rangeof 1×10¹⁴ cm⁻² to 1×10¹⁵ cm⁻².

(f) FIG. 14 shows the relationship between the dose in the floating gateand the lifetime of the tunnel oxide film, i.e., the quantity of passingcharge Q_(bd) allowable until occurrence of a breakdown of the tunneloxide film. In this experiment, the sample employed is fabricated in thesame manner as for the experiment (d).

According to the quantity of charge Q_(p) (process-induced charge)passing through the tunnel oxide film in a manufacturing step performedafter formation of the tunnel oxide film, the quantity of passing chargeQ_(bd) becomes lower than the quantity of intrinsic charge Q_(i)determined by a factor such as an oxide film formation method.Therefore, a limitation is imposed on the allowable number ofwrite/erase operations in the flash-type EEPROM which is affected by thequantity of passing charge Q_(bd), and there is a possibility that thedata retaining characteristic may deteriorate (occurrence of single-bitcharge loss).

As shown in FIG. 14, the quantity of passing charge Q_(bd) does notdecrease under condition that a dose in the floating gate is in therange of 1×10¹⁴ to 5×10¹⁵ cm⁻². This means that the number ofwrite/erase operations and the data retaining characteristic ismaintained at satisfactory levels.

(g) FIG. 15 shows the relationship between the data retainingcharacteristic of the memory cell and the dose in the floating gate. Inthis experiment, the sample employed is a flash-type EEPROM of 1M bitswhich is fabricated in the same manner as for the experiment (d).

In the experiment, data was written into the sample, and then the rateof data retention was determined while maintaining the sample at aconstant temperature of 250° C. in a thermostatic chamber.

As shown in FIG. 15, the data retaining characteristic does not decreaseunder the condition that a dose in the floating gate is in the range of1×10¹⁴ to 5×10¹⁵ cm^(−2.)

While the present invention has been described in detail with respect tospecific embodiments thereof, it is to be understood that the inventionis not limited by any of the details of description and that variouschanges and modifications may be made without departing from the spiritand scope of the present invention.

What is claimed is:
 1. A nonvolatile semiconductor memory device,comprising: a semiconductor substrate; and a memory transistor includinga source region and a drain region which are impurity diffusion layersformed in said semiconductor substrate, a tunnel insulating layer formedon said semiconductor substrate, and a gate electrode of a stackedstructure having a floating gate, a dielectric layer and a control gatewhich are layered on said tunnel insulating layer, wherein said floatinggate is formed of a polysilicon layer having an impurity concentrationof 1×10¹⁹ to 1×10²⁰ cm⁻³.
 2. A nonvolatile semiconductor memory deviceaccording to claim 1, wherein said impurity concentration is in a rangeof 1×10¹⁹ to 5×10¹⁹ cm⁻³.
 3. A nonvolatile semiconductor memory deviceaccording to claim 1, wherein, denoting the impurity concentration of apolysilicon layer constituting said floating gate as C_(FG) and theimpurity concentration of a polysilicon layer constituting said controlgate as C_(CG), the following relational expression is satisfied:0.3×C_(FG)≦C_(CG)≦0.8×C_(FG).
 4. A nonvolatile semiconductor memorydevice according to claim 1, wherein said source region has anoverlapping region with said floating gate, said overlapping regionbeing 25 to 45% of a bottom surface of said floating gate.
 5. Anonvolatile semiconductor memory device according to claim 1, whereinsaid source region comprises a first diffusion region having a highimpurity concentration, and a second diffusion region disposed outsidesaid first diffusion region and having an impurity concentration lowerthan that of said first diffusion region.
 6. A method of manufacturing anonvolatile semiconductor memory device, comprising steps of: (a)forming a tunnel insulating layer, a first polysilicon layer for afloating gate, a dielectric layer, and a second polysilicon layer for acontrol gate in a memory transistor formation region on a semiconductorsubstrate; (b) forming a gate electrode of a stacked structure includinga floating gate, a dielectric layer, and a control gate by patterningsaid second polysilicon layer, said dielectric layer, and said firstpolysilicon layer; and (c) forming a source region and a drain region insaid semiconductor substrate by doping with an impurity; wherein, insaid step (a), said first polysilicon layer is doped with an impurity ata concentration of 1 ×10¹⁹ to 1×10²⁰ cm⁻³.
 7. A method of manufacturinga nonvolatile semiconductor memory device according to claim 6, whereina concentration of said impurity is in a range of 1×10¹⁹ to 5×10¹⁹ cm⁻³.8. A method of manufacturing a nonvolatile semiconductor memory deviceaccording to claim 6, wherein said first polysilicon layer is formed bydoping a polysilicon layer with an impurity ion at a dose ranging from1×10¹⁴ to 1×10¹⁵ cm⁻².
 9. A method of manufacturing a nonvolatilesemiconductor memory device according to claim 8, wherein said firstpolysilicon layer is formed by doping a polysilicon layer with animpurity ion at a dose ranging from 1 ×10¹⁴ to 5 ×10¹⁵ cm⁻².
 10. Amethod of manufacturing a nonvolatile semiconductor memory deviceaccording to claim 6, wherein, denoting an impurity concentration of apolysilicon layer constituting said floating gate as C_(FG) and animpurity concentration of a polysilicon layer constituting said controlgate as C_(CG), the following relational expression is satisfied:0.3×C_(FG)≦C_(CG)≦0.8×C_(FG).
 11. A method of manufacturing anonvolatile semiconductor memory device according to claim 6, whereinsaid source region comprises a first diffusion region having a highimpurity concentration, and a second diffusion region disposed outsidesaid first diffusion region and having an impurity concentration lowerthan that of said first diffusion region.
 12. A method of manufacturinga nonvolatile semiconductor memory device according to claim 6, furthercomprising a step (d), before said step (c), for forming a protectiveoxide layer to cover exposed surface of at least said tunnel insulatinglayer and gate electrode.
 13. A method of manufacturing a nonvolatilesemiconductor memory device according to claim 12, wherein, in said step(d), formation of said protective oxide layer on at least a side wall ofsaid gate electrode is omitted.